There are many well-known techniques to generate and modulate a clock or carrier waveform in various domains, often the analog domain. Existing analog techniques involve the use of an analog delay line used in open loop, but such a technique has the drawback of relatively poor timing stability. Existing digital techniques generally rely on integer division by a counter utilizing either rising or falling edges (but not both) of a single input clock. Greater timing resolution requires increased input clock frequency. It is desirable to provide a digital technique to generate and modulate a clock carrier waveform that achieves improved timing resolution without increasing the input clock frequency.